1. Field
This disclosure relates generally to integrated circuit design verification and, more specifically, to integrated circuit design verification through forced clock glitches.
2. Related Art
Verifying clock integrity of an integrated circuit (IC) design can be challenging. For example, timing requirements of edge-trigger devices (e.g., flip-flops) must be met and setup/hold times of edge-triggered devices must satisfy design requirements in order to prevent metastability, which may cause an IC, when fabricated, to behave incorrectly. Metastability, which is a special case of non-determinism, is a condition where a bi-stable state is neither ‘0’ nor ‘1’ for a period of time. Clock glitches may cause a circuit to violate timing requirements and trigger metastability. In general, increased circuit complexity and aggressive clock gating techniques make clock distribution prone to clock glitches. Traditionally, incorrect timing behaviour has normally only been visible at the gate-level or at the silicon-level. In general, when incorrect timing behaviour is not detected until the gate-level or the silicon-level, a large amount of resources have been wasted. Conventional register-transfer level (RTL) verification has not been able to detect clock glitch induced metastability, as conventional RTL verification is zero delay and has typically not implemented timing checks.
RTL is a design abstraction that models a synchronous digital IC in terms of the flow of digital signals (data) between hardware registers and the logical operations performed on those signals. RTL abstraction is used in hardware description languages (HDLs) to create high-level representations of an IC, from which lower-level representations and ultimately actual silicon can be derived. Design at the RTL stage is the typical practice in modern digital IC design. A synchronous random circuit includes two kinds of elements (i.e., registers and combinational logic). Registers (usually implemented as D flip-flops as an example) synchronize operation of a circuit to edges of a clock signal and are the only elements in the circuit that have memory properties. Combinational logic performs all the logical functions in the circuit and typically only includes logic gates (e.g., AND gates, NAND gates, OR gates, NOR gates, etc.). When designing digital ICs with an HDL, IC designs are engineered at a higher level of abstraction than a transistor-level or a gate-level. In HDLs, a designer declares the registers and describes the combinational logic by using constructs (e.g., if-then-else statements and arithmetic operations) that are familiar in programming languages. In general, RTL focuses on describing the flow of signals between registers.